1. Technical Field of the Invention
The present invention relates to a compensation circuit for a power transistor, and particularly to a compensation circuit for biasing a power transistor to offset unwanted variations in the operating characteristics thereof.
2. Background of the Invention
Power transistors have been utilized for years in providing relatively sizeable current levels for applications in a number of markets, such as audio, video, consumer, multi-media and wireless communications. Concerning wireless communications, power transistors are commonly used in amplification stages for radio base station amplifiers and other radio frequency (RF) applications. Such transistors, when used for power amplification at high frequencies, need to meet numerous detailed requirements for output power, gain, robustness, efficiency, stability, bandwidth, etc., at a specified supply voltage and operating frequency.
At least one type of power transistor utilized in power applications is a field effect transistor and particularly a MOS transistor. Like the performance of most all transistors, the operating characteristics of MOS power transistors are affected by a number of conditions and/or phenomenon. Temperature and process variations may cause changes in the operating characteristics of a power transistor. In addition, MOS transistors, such as lateral diffused MOS (LDMOS) transistors, may exhibit gate oxide charging over time. Specifically, electrons in the channel region of a MOS transistor can be accelerated by the source-drain electric field, surmount the channel region-gate oxide interfacial barrier and become trapped in the gate oxide region of the MOS transistor. The trapped electrons in the gate oxide region change the device characteristics of the MOS transistor, including shifting the threshold voltage thereof. For an enhancement mode MOS transistor, the threshold voltage increases as the number of charges in the gate oxide region increases. This shift in the threshold voltage of a MOS transistor may cause a dramatic change in the quiescent current level thereof. A change in the quiescent current level effects the overall linearity performance and small signal gain of the MOS transistor. As can be seen, there is a need to account for changes in the performance of MOS transistors caused by any of a number of phenomenon.